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| asahi kasei [AK4122] ms0267-e-02 2004/07 - 1 - general description the AK4122 is a digital sample rate converter (src) with the digital audio receiver (dir). the input sample rate ranges from 8khz to 96khz. the output sample rate is 32khz, 44.1khz, 48khz or 96khz. by using the AK4122, the system can take very simp le configuration because the AK4122 has an internal pll and does not need any master clock at slave m ode. then the AK4122 is suit able for the application interfacing to different sample rate s like car audio, dvd recorder, etc. features 1. src ? asynchronous sample rate converter ? input sample rate range (fsi) : 8khz 96khz ? output sample rate (fso) : 32khz, 44.1khz, 48khz, 96khz ? input to output sample rate ratio : 0.33 to 6 ? thd+n : ? 113db ? i/f format : msb justified, lsb justified (16/24bit) and i 2 s compatible ? clock for master mode : 256/384/512/768fs ? src bypass mode ? soft mute function 2. dir ? 4-channel inputs selector & 1-channel through output ? aes3, iec60958, s/pdif, eiaj cp1201 compatible ? low jitter analog pll ? pll lock range : 32khz 96khz ? auto detection - non-pcm bit stream - dts-cd bit stream - validity flag - sampling frequency (32khz, 44.1khz, 48khz, 88.2khz, 96khz) - unlock & parity error - dat start id ? 40-bit channel status buffer ? burst preamble bit pc, pd buffer for non-pcm bit streams ? q-subcode buffer for cd bit streams 3. 4-wire serial p interface 4. power supply ? avdd: 3.0 3.6v (typ. 3.3v) ? dvdd: 3.0 3.6v (typ. 3.3v) 5. ta = ? 10 70 c 6. package : 48pin lqfp 24-bit 96khz src with dir AK4122
asahi kasei [AK4122] ms0267-e-02 2004/07 - 2 - ? block diagram rx2 rx2 pdn rx1 rx1 ips1-0 serial audio i/f lrck1 sdti lrck1 sdti bick1 bick1 serial audio i/f lrck2 sdtio lrck2 sdtio bick2 bick2 mclk2 lrck bick sdto lrck bick sdto omclk smute control register cdto cdti cclk csn avdd avss dvdd dvss m/s2 m/s3 src pll serial audio i/f de-em filter port1 port2 port3 rx3 rx3 rx4 rx4 dir tx tx isel1-0 osel byps int0 int1 r filt int2 ops1-0 block diagram asahi kasei [AK4122] ms0267-e-02 2004/07 - 3 - ? ordering guide AK4122vq ? 10 +70 c 48pin lqfp (0.5mm pitch) akd4122 evaluation board for AK4122 ? pin layout cdti cclk 48 47 1 46 45 44 43 42 41 40 39 38 36 35 34 33 32 31 30 29 28 27 26 23 22 21 20 19 18 17 16 15 14 13 2 3 4 5 6 7 8 9 10 11 AK4122vq top view cdto tst1 int2 tst2 tst3 m/s2 m/s3 smute tst4 tst5 avss pdn lrck1 bick1 sdti dvss dvdd mclk2 lrck2 bick2 sdtio csn bvss dvdd dvss omclk lrck bick sdto tx int1 12 filt 24 25 r 37 int0 tst6 avdd avss rx1 tst7 rx2 tst8 rx3 tst9 rx4 tst10 tst11 asahi kasei [AK4122] ms0267-e-02 2004/07 - 4 - pin/function no. pin name i/o function 1 cdti i control data input pin 2 cdto o control data output pin 3 tst1 o test 1 pin 4 int2 o interrupt 2 pin 5 tst2 o test 2 pin 6 tst3 i test 3 pin this pin should be connected to dvss. 7 m/s2 i master / slave mode pin for port2 ?h? : master mode, ?l? : slave mode 8 m/s3 i master / slave mode pin for port3 ?h? : master mode, ?l? : slave mode 9 smute i soft mute pin ?h? : soft mute, ?l? : normal operation 10 tst4 i test 4 pin this pin should be connected to avss. 11 tst5 i test 5 pin this pin should be connected to avss. 12 filt o pll loop filter pin 470 ? 5% resistor and 2.2 f 50% ceramic capacitor in parallel with a 2.2nf 50% ceramic capacitor should be connected to avss externally. 13 avss - analog ground pin 14 avdd - analog power supply pin, 3.0 3.6v 15 tst6 i test 6 pin this pin should be connected to avss. 16 rx1 i receiver input 1 pin with am p for 0.2vpp (internal biased pin) 17 tst7 i test 7 pin this pin should be connected to avss. 18 rx2 i receiver input 2 pin with am p for 0.2vpp (internal biased pin) 19 tst8 i test 8 pin this pin should be connected to avss. 20 rx3 i receiver input 3 pin with am p for 0.2vpp (internal biased pin) 21 tst9 i test 9 pin this pin should be connected to avss. 22 rx4 i receiver input 4 pin with am p for 0.2vpp (internal biased pin) 23 tst10 i test 10 pin this pin should be connected to avss. 24 tst11 o test 11 pin note: all input pins except internal biased pins should not be left floating. asahi kasei [AK4122] ms0267-e-02 2004/07 - 5 - 25 r - external resistor pin 12k ? 5% resistor should be connected to avss externally. 26 avss - analog ground pin 27 pdn i power-down mode pin ?h?: power up, ?l?: power down reset and initializes the control register. 28 lrck1 i input channel clock pin 29 bick1 i audio serial data clock pin 30 sdti i audio serial data input pin 31 dvss - digital ground pin 32 dvdd - digital power supply pin, 3.0 3.6v 33 mclk2 i master clock input pin 34 lrck2 i/o input / output channel clock pin 35 bick2 i/o audio serial data clock pin 36 sdtio i/o audio serial data input / output pin 37 int0 o interrupt 0 pin 38 int1 o interrupt 1 pin 39 tx o transmitter output pin 40 sdto o audio serial data output pin 41 bick i/o audio serial data clock pin 42 lrck i/o output channel clock pin 43 omclk i master clock input pin 44 dvss - digital ground pin 45 dvdd - digital power supply pin, 3.0 3.6v 46 bvss - substrate ground pin this pin should be connected to avss. 47 csn i chip select pin 48 cclk i control data clock pin note: all input pins except internal biased pins should not be left floating. asahi kasei [AK4122] ms0267-e-02 2004/07 - 6 - ? handling of unused pins the unused digital i/o pins should be processed appropriately as below. classification pin name setting port1 bick1, lrck1, sdti these pins should be connected to dvss. mclk2 this pin should be connected to dvss. bick2, lrck2 these pins should be connected to dvss in slave mode or open in master mode. sdtio this pin should be connected to dvss. port2 m/s2 this pin should be connected to dvdd or dvss. omclk this pin should be connected to dvss. bick, lrck these pins should be connected to dvss in slave mode or open in master mode. sdto this pin should be open. port3 m/s3 this pin should be connected to dvdd or dvss. rx1, rx2, rx3, rx4 these pins should be open. dir int0, int1, int2, tx these pins should be open. csn, cclk, cdti these pins should be connected to dvss. control port cdto this pin should be open. other smute this pin should be connected to dvss. tst1, tst2, tst11 these pins should be open. tst3 this pin should be connected to dvss. test tst4, tst5, tst6, tst7, tst8, tst9, tst10 these pins should be connected to avss. asahi kasei [AK4122] ms0267-e-02 2004/07 - 7 - absolute maximum ratings (avss, bvss, dvss=0v; note 1) parameter symbol min max units power supplies: analog digital |bvss ? dvss| (note 2) avdd dvdd ? gnd ? 0.3 ? 0.3 - 4.6 4.6 0.3 v v v input current, any pin except supplies iin - 10 ma digital input voltage 1 (except rx1-4 pins) vind1 ? 0.3 dvdd+0.3 v digital input voltage 2 (rx1-4 pins) vind2 ? 0.3 avdd+0.3 v ambient temperature (power applied) ta ? 10 70 c storage temperature tstg ? 65 150 c note 1. all voltages with respect to ground. note 2. avss, bvss and dvss must be connected to the same ground. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (avss, bvss, dvss=0v; note 1) parameter symbol min typ max units power supplies (note 3) analog digital avdd dvdd 3.0 3.0 3.3 3.3 3.6 avdd v v note 1. all voltages with respect to ground. note 3. the power up sequence be tween avdd and dvdd is not critical. warning: akm assumes no responsibility for the us age beyond the conditions in this datasheet. asahi kasei [AK4122] ms0267-e-02 2004/07 - 8 - src characteristics (ta=25 c; avdd=dvdd=3.3v; avss=bvss=dvss=0v; data = 24b it; measurement bandwid th = 20hz ~ fso/2; unless otherwise specified.) parameter symbol min typ max units src characteristics: resolution (note 4) 24 bits input sample rate fsi 8 96 khz output sample rate fso 32 96 khz thd+n (input = 1khz, 0dbfs, note 5) fso/fsi = 44.1khz/48khz fso/fsi = 48khz/44.1khz fso/fsi = 32khz/48khz fso/fsi = 96khz/32khz worst case (fso/fsi = 48khz/8khz) - - - - - ? 113 ? 113 ? 114 ? 111 - - - - - ? 103 db db db db db dynamic range (input = 1khz, ? 60dbfs, note 5) fso/fsi = 44.1khz/48khz fso/fsi = 48khz/44.1khz fso/fsi = 32khz/48khz fso/fsi = 96khz/32khz worst case (fso/fsi = 32khz/44.1khz) dynamic range (input = 1khz, ? 60dbfs, a-weighted, note 5) fso/fsi = 44.1khz/48khz - - - - 112 - 114 115 115 116 - 117 - - - - - - db db db db db db ratio between input and output sample rate (note 6) fso/fsi 0.33 6 - note 4. input data for src corresponds to 24bit data. when lsb 4bit data is input, the AK4122 calculates as ?0? data because src is 20bit calculation. therefore, src outputs ?0? data. note 5. measured by rohde & schwarz up d04, rejection filter = wide, 8192point fft. note 6. the ?0.33? is the ratio of fso/fsi when fsi is 96khz and fso is 32khz. the ?6? is the ratio of fso/fsi when fsi is 8khz and fso is 48khz. s/pdif receiver characteristics (ta=25 c; avdd, dvdd=3.0 3.6v) parameter symbol min typ max units input resistance zin - 10 - k ? input voltage vth 200 mvpp input sample frequency fs 32 - 96 khz asahi kasei [AK4122] ms0267-e-02 2004/07 - 9 - filter characteristics (ta=25 c; avdd, dvdd=3.0 3.6v; dem=off) parameter symbol min typ max units digital filter 0.985 fso/fsi 6.000 pb 0 0.4583fsi khz 0.905 fso/fsi < 0.985 pb 0 0.4167fsi khz 0.714 fso/fsi < 0.905 pb 0 0.3195fsi khz 0.656 fso/fsi < 0.714 pb 0 0.2852fsi khz 0.536 fso/fsi < 0.656 pb 0 0.2245fsi khz 0.492 fso/fsi < 0.536 pb 0 0.2003fsi khz 0.452 fso/fsi < 0.492 pb 0 0.1781fsi khz passband ? 0.001db 0.333 fso/fsi < 0.452 pb 0 0.1092fsi khz 0.985 fso/fsi 6.000 sb 0.5417fsi khz 0.905 fso/fsi < 0.985 sb 0.5021fsi khz 0.714 fso/fsi < 0.905 sb 0.3965fsi khz 0.656 fso/fsi < 0.714 sb 0.3643fsi khz 0.536 fso/fsi < 0.656 sb 0.2974fsi khz 0.492 fso/fsi < 0.536 sb 0.2732fsi khz 0.452 fso/fsi < 0.492 sb 0.2510fsi khz stopband 0.333 fso/fsi < 0.452 sb 0.1822fsi khz passband ripple pr 0.01 db stopband attenuation sa 96 db group delay (note 7) gd - 58.5 - 1/fs note 7. this value is the time from the rising edge of lrck after data is input to rising edge of lrck after data is output, when lrck for output data corresponds with lrck for input. dc characteristics (ta=25 c; avdd, dvdd=3.0 3.6v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 70%dvdd - - - - 30%dvdd v v high-level output voltage (iout= ? 400 a) low-level output voltage (iout=400 a) voh vol dvdd ? 0.4 - - - - 0.4 v v input leakage current iin - - 10 a parameter min typ max units power supply current normal operation (pdn pin = ?h?) (note 8) fsi=fso=48khz at slave mode: avdd=dvdd=3.3v fsi=fso=96khz at master mode: avdd=dvdd=3.3v fsi=fso=96khz at master mode: avdd=dvdd=3.6v power down (pdn pin = ?l?) (note 9) avdd+dvdd 15 29 - 10 - - 45 100 ma ma ma a note 8. typ and max values are the va lue of avdd+dvdd in each power supply voltage. power supply current of each path @slave mode, avdd=dvdd=3.3v, fsi=fso=48khz 1. port1 src port3: avdd=5ma(typ), dvdd=10ma(typ) 2. port2 src port3: avdd=5ma(typ), dvdd=10ma(typ) 3. dir src port3: avdd=6ma(typ), dvdd=9ma(typ) note 9. all digital input pins are held dvss. asahi kasei [AK4122] ms0267-e-02 2004/07 - 10 - switching characteristics (ta=25 c; avdd, dvdd=3.0 3.6v; c l =20pf) parameter symbol min typ max units master clock timing frequency pulse width low pulse width high fclk tclkl tclkh 8.192 0.4/fclk 0.4/fclk 36.864 mhz ns ns lrck for input data (lrck1, lrck2) frequency duty cycle fs duty 8 48 50 96 52 khz % lrck for output data (lrck, lrck2) frequency (note 10) duty cycle slave mode master mode fs duty duty 32 48 50 50 96 52 khz % % s/pdif clock recover frequency fpll 32 96 khz audio interface timing input for port1 bick1 period bick1 pulse width low pulse width high lrck1 edge to bick1 ? ? (note 11) bick1 ? ? to lrck1 edge (note 11) sdti hold time from bick1 ? ? sdti setup time to bick1 ? ? tbck tbckl tbckh tlrb tblr tsdh tsds 1/64fs 65 65 30 30 30 30 ns ns ns ns ns ns ns input for port2 (slave mode) bick2 period bick2 pulse width low pulse width high lrck2 edge to bick2 ? ? (note 11) bick2 ? ? to lrck2 edge (note 11) sdtio hold time from bick2 ? ? sdtio setup time to bick2 ? ? tbck tbckl tbckh tlrb tblr tsdh tsds 1/64fs 65 65 30 30 30 30 ns ns ns ns ns ns ns output for port2 (slave mode) bick2 period bick2 pulse width low pulse width high lrck2 edge to bick2 ? ? (note 11) bick2 ? ? to lrck2 edge (note 11) lrck2 to sdtio (msb) (except i 2 s mode) bick2 ? ? to sdtio tbck tbckl tbckh tlrb tblr tlrs tbsd 1/64fs 65 65 30 30 30 30 ns ns ns ns ns ns ns note 10. min value is 8khz at bypass mode. note 11. bick1 rising edge must not occur at the same time as lrck1 edge. bick2 rising edge must not occur at the same time as lrck2 edge. asahi kasei [AK4122] ms0267-e-02 2004/07 - 11 - parameter symbol min typ max units output for port3 (slave mode) bick period bick pulse width low pulse width high lrck edge to bick ? ? (note 11) bick ? ? to lrck edge (note 11) lrck to sdto (msb) (except i 2 s mode) bick ? ? to sdto tbck tbckl tbckh tlrb tblr tlrs tbsd 1/64fs 65 65 30 30 30 30 ns ns ns ns ns ns ns output for port2 (master mode) bick2 frequency bick2 duty bick2 ? ? to lrck2 bick2 ? ? to sdtio fbck dbck tmblr tbsd ? 20 ? 20 64fs 50 20 30 hz % ns ns output for port3 (master mode) bick frequency bick duty bick ? ? to lrck bick ? ? to sdto fbck dbck tmblr tbsd ? 20 ? 20 64fs 50 20 30 hz % ns ns control interface timing cclk period (note 12) cclk pulse width low pulse width high cdti setup time cdti hold time csn ?h? time csn ? ? to cclk ? ? cclk ? ? to csn ? ? cdto delay csn ? ? to cdto hi-z tcck tcckl tcckh tcds tcdh tcsw tcss tcsh tdcd tccz 200 80 80 40 40 150 50 50 1000 45 70 ns ns ns ns ns ns ns ns ns ns reset timing pdn pulse width (note 13) tpd 150 ns note 11. bick rising edge must not occur at the same time as lrck edge. note 12. in case of using int2. when int2 is not used, the max value is not limited. note 13. the AK4122 can be reset by bringing the pdn pin = ?l?. asahi kasei [AK4122] ms0267-e-02 2004/07 - 12 - ? timing diagram 1/fclk mclk tclkh tclkl vih vil 1/fs lrck vih vil tbck bick tbckh tbckl vih vil clock timing lrck vih vil tblr bick vih vil tlrs sdto 50%dvdd tlrb tbsd tsds sdti vil tsdh vih audio interface timing (slave mode) note : bick shows bick1 of port1, bick2 of port2 and bick of port3. lrck shows lrck1 of port1, lrck2 of port2 and lrck of port3. sdti shows sdti of port1 or sdtio of port2 that is used as input port. sdto shows sdto of port3 or sdtio of port2 that is used as output port. asahi kasei [AK4122] ms0267-e-02 2004/07 - 13 - lrck bick 50%dvdd sdto 50%dvdd tbsd tsds sdti vil tsdh vih tmblr dbck 50%dvdd audio interface timing (master mode) note : bick shows bick1 of port1, bick2 of port2 and bick of port3. lrck shows lrck1 of port1, lrck2 of port2 and lrck of port3. sdti shows sdti of port1 or sdtio of port2 that is used as input port. sdto shows sdto of port3 or sdtio of port2 that is used as output port. csn vih vil tcss cclk tcds vih vil cdti vih tcckh tcckl tcdh vil c1 c0 r/w cdto hi-z write/read command input timing asahi kasei [AK4122] ms0267-e-02 2004/07 - 14 - csn vih vil tcsh cclk vih vil cdti vih tcsw vil d1 d0 cdto hi-z d2 write data input timing csn vih vil cclk vih vil cdti vih vil a0 cdto a1 50%dvdd tdcd d7 d6 hi-z read data output timing 1 asahi kasei [AK4122] ms0267-e-02 2004/07 - 15 - csn vih vil tcsh cclk vih vil cdti vih tcsw vil cdto 50%dvdd d2 d1 d0 tccz hi-z read data output timing 2 tpd pdn vil power down & reset timing asahi kasei [AK4122] ms0267-e-02 2004/07 - 16 - operation overview ? internal signal path the input source of the src can be switched between the outputs of the dir, port1 or port2. the input source of the port2 and port3 can be switched between the outputs of the src or bypass. when port2 is used as input port, port2 cannot use as output port. the signal path should be controlled during pwn bit = ?0?. the switch names (isel1-0 bits etc) in figure 1 correspond to the register bits that control the switch function. refer to table 1. serial audio i/f serial audio i/f port1 port2 dir isel1-0 src pll serial audio i/f de-em filter port3 osel byps figure 1. connection input source & output source input port src / bypass output port mode isel1-0 bit byps bit osel bit path 0 00 : port1 port1 src port3 1 01 : port2 port2 src port3 2 10 : dir 0 : src dir src port3 3 00 : port1 port1 port3 4 01 : port2 port2 port3 5 10 : dir 1 : bypass 0 : port3 (note 1) dir port3 6 00 : port1 port1 src port2 7 10 : dir 0 : src dir src port2 8 00 : port1 port1 port2 9 10 : dir 1 : bypass 1 : port2 (note 2) dir port2 table 1. path select default is mode 0. (path : port1 src port3) after pdn pin = ?l? ?h?, sdtio pin of port2 is the input pin. the dif1-0 bits of the port1 should be set a value except ?10? (i 2 s compatible) when the dir is selected as an input port. refer to table 6 and 7 for master/slave mode setting. asahi kasei [AK4122] ms0267-e-02 2004/07 - 17 - note 1. in this case, port2 is input port. if port2 is unused, the digital i/o pins should be processed appropriately by table 2. m/s2 pin mode unused pin pin i/o setting mclk2 i this pin should be connected to dvss. bick2 i this pin should be connected to dvss. lrck2 i this pin should be connected to dvss. l slave sdtio i this pin should be connected to dvss. mclk2 i this pin should be connected to dvss. bick2 o this pin should be open. lrck2 o this pin should be open. h master sdtio i this pin should be connected to dvss. table 2. pin setting for port2 note 2. in this case, port3 is output port. if port3 is unused, the digital i/o pins should be processed appropriately by table 3. m/s3 pin mode unused pin pin i/o setting omclk i this pin should be connected to dvss. bick i this pin should be connected to dvss. lrck i this pin should be connected to dvss. l slave sdto o this pin should be open. omclk i this pin should be connected to dvss. bick o this pin should be open. lrck o this pin should be open. h master sdto o this pin should be open. table 3. pin setting for port3 ? system clock port1 can be operated in slave mode only. port2 and port3 work in master mode and slave mode. internal system clock is created by internal pll using lrck1, lrck2 or lrck of dir. the mclk is not needed when port2 and port3 are in slave mode and then please set mclk2 pin and omclk pin to dvss. however, when port2 and port3 are used in master mode, mclk2 pin and omclk pin should be supplied to mclk. the m/s2 pin and m/s3 pin select between master and slave mode. table 4 and 5 show setting of mclk frequency that port2 and port3 are master mode. in case of detecting the sampling frequency by mclk when dir is used, mclk (mclk2 or omclk) of selected output port (port2 or port3) should be input. mclk2 icks1 icks0 32khz fs 48khz 48khz < fs 96khz 0 0 256fs 256fs 0 1 384fs 384fs 1 0 512fs n/a 1 1 768fs n/a default table 4. mclk2 frequency select for master mode omclk ocks1 ocks0 32khz fs 48khz 48khz < fs 96khz 0 0 256fs 256fs 0 1 384fs 384fs 1 0 512fs n/a 1 1 768fs n/a default table 5. omclk frequency select for master mode asahi kasei [AK4122] ms0267-e-02 2004/07 - 18 - ? master mode and slave mode when port2 and port3 are used as output port, the m/s2 pin and m/s3 pin select either master or slave mode. ?h? is master mode, ?l? is slave mode. in master mode, mclk should be input and the AK4122 outputs bick and lrck. in slave mode, bick and lrck are input externally and mclk is not needed. if port2 is used as input port, m/s2 pin should be set ?h? or ?l?. m/s2 pin byps bit data i/o mode bick, lrck l 0 i/o slave, src input available l 1 output not available input h 0 i/o master, src h 1 i/o master, bypass output table 6. master mode/slave mode for port2 m/s3 pin byps bit data i/o mode bick, lrck l 0 output slave, src l 1 output not available input h 0 output master, src h 1 output master, bypass output table 7. master mode/slave mode for port3 ? audio interface format the audio interface should be controlled during pwn bit = ?0?. when in bypa ss mode, bick1, bick2 and bick are fixed to 64fs. (1) port1 four kinds of data formats can be chosen with the dif1-0 bits (table 8). in all modes, the serial data is in msb first, 2?s compliment format. the sdti is latched on the rising edge of bick1. port1 corresponds to slave mode only. mode dif1 dif0 input format lrck bick 0 0 0 16bit, lsb justified h/l 32fs 1 0 1 24bit, msb justified h/l 48fs 2 1 0 24bit, i 2 s compatible l/h 48fs 3 1 1 24bit, lsb justified h/l 48fs default table 8. audio interface format for port1 note: the dif1-0 bits of the port1 should be set a value except ?10? (i 2 s compatible) when the dir is selected as an input port. lrck bick(32fs) 0 110 2 3 9 1112131415 0 12 3 1 0 10 9 1112131415 sdti(i) don't care 1 0 15 14 13 210 15 14 13 12 12 don't care sdti-15:msb, 0:lsb sdti(i) 15 14 13 76543 210 15 14 13 15 76543 210 bick(64fs) 0 118 2 3 19 20 31 0 1 2 3 1 0 18 19 20 31 17 17 lch data rch data figure 2. mode 0 timing asahi kasei [AK4122] ms0267-e-02 2004/07 - 19 - lrck bick(64fs) 0 1 2202124310 12 1 0 22 20 21 31 24 22 23 23 sdti(i) don't care 0 0 23:msb, 0:lsb lch data rch data don't care 4321 23 22 23 22 23 1 2 3 4 figure 3. mode 1 timing lrck bick(64fs) 0 1 225 21 24 0 12 1 0 22 25 21 24 22 23 23 3 sdti(i) don't care 0 0 23:msb, 0:lsb lch data rch data don't care 4321 23 22 23 22 1 2 3 4 figure 4. mode 2 timing lrck bick(64fs) 0 1 224310 12 1 0 31 24 89 89 sdti(i) don't care 0 8 10 23:msb, 0:lsb lch data rch data 23 8 don't care 23 1 figure 5. mode 3 timing (2) port2 four kinds of data formats can be chosen with the idif1-0 bits (table 9). in all modes, the serial data is in msb first, 2?s compliment format. if port2 is selected the output port, the sdtio is clocked out on the falling edge of bick2, and if port2 is selected the input port, the sdtio is latched on the rising edge of bick2. th e audio interface supports both master and slave modes. in master mode, bick2 and lrck 2 are output with the bick2 frequency fixed to 64fs and the lrck2 frequency fixed to 1fs. mode idif1 idif0 output format input format lrck bick 0 0 0 24bit, msb justified 16bit, lsb justified h/l 32fs 1 0 1 24bit, msb justified 24bit, msb justified h/l 48fs 2 1 0 24bit, i 2 s compatible 24bit, i 2 s compatible l/h 48fs 3 1 1 24bit, msb justified 24bit, lsb justified h/l 48fs default table 9. audio interface format for port2 asahi kasei [AK4122] ms0267-e-02 2004/07 - 20 - lrck bick(32fs) sdtio(o) sdtio(i) 0 23 22 15 14 110 21 13 23 15 76543 210 14 13 12 11 98 10 9 1112131415 0 12 3 23 22 21 15 14 13 15 14 13 12 11 98 10 1 0 23 15 76543 210 10 9 1112131415 bick(64fs) 0 118 2 3 19 20 31 0 1 2 3 1 0 18 19 20 31 sdtio(o) sdtio(i) 23 22 21 don't care 10 7 23 22 21 15 14 13 23 210 17 6543 15 14 13 12 76543 17 12 don't care sdtio-23:msb, 0:lsb sdtio-15:msb, 0:lsb lch data rch data figure 6. mode 0 timing lrck bick(64fs) sdtio(o) sdtio(i) 0 23 22 don't care 1 2 4 0 0 20 21 24 31 0 12 23 22 0 1 0 23 0 22 20 21 31 23:msb, 0:lsb lch data rch data don't care 24 321 4321 23 22 22 23 23 22 23 23 1 2 3 4 1 2 3 4 figure 7. mode 1 timing lrck bick(64fs) sdtio(o) sdtio(i) 0 23 22 don't care 1 2 4 0 0 25 21 24 0 12 23 22 0 1 0 0 22 25 21 23:msb, 0:lsb lch data rch data don't care 24 321 4321 23 22 22 23 23 22 23 1 2 3 4 1 2 3 4 3 figure 8. mode 2 timing lrck bick(64fs) sdtio(o) sdtio(i) 0 23 22 don't care 1 2 16 0 15 0 24 31 0 12 23 22 16 15 0 1 0 23 8 10 31 23:msb, 0:lsb lch data rch data 23 8 don't care 23 24 89 1 89 figure 9. mode 3 timing asahi kasei [AK4122] ms0267-e-02 2004/07 - 21 - (3) port3 two kinds of data formats can be chosen with the odif bit (table 10). in both modes, the serial data is in msb first, 2?s compliment format. the sdto is clocked out on the falling e dge of bick. the audio interface supports both master and slave modes. in master mode, bick and lrck are output with the bick frequency fixed to 64fs and the lrck frequency fixed to 1fs. mode odif output format lrck bick 0 0 24bit, msb justified h/l 48fs 1 1 24bit, i 2 s compatible l/h 48fs default table 10. audio interface format for port3 lrck bick(64fs) 0 118 2 3 19 20 31 0 1 2 3 1 0 18 19 20 31 sdto(o) 23 22 21 7 23 22 21 23 17 6543 76543 17 sdto-23:msb, 0:lsb lch data rch data figure 10. mode 0 timing lrck bick(64fs) sdto(o) 0 23 22 1 2 4 0 25 21 24 0 12 23 22 0 1 0 22 25 21 24 321 22 23 23 1 2 3 4 3 23:msb, 0:lsb lch data rch data figure 11. mode 1 timing asahi kasei [AK4122] ms0267-e-02 2004/07 - 22 - ? soft mute operation soft mute operation is performed in the digital domain of the src output. soft mute can be controlled by smute bit or smute pin. the smute bit and smute pin are ored between pin and register. when smute bit goes ?1? or smute pin goes ?h?, the src output data is attenuated by ? within 1024 lrck cycles. when the smute bit returned ?0? and smute pin goes ?l? the mute is cancelled and th e output attenuation gradually changes to 0db during 1024 lrck cycles. if the soft mute is cancelled before mute state after starting of the operation, the attenuation is discontinued and returned to 0db by the same cycles. the soft mute is effective for changing the signal source. smute a ttenuation datt level - gd gd (1) (2) (3) sdtio / sdto figure 12. soft mute function (1) the output data is attenuated by ? during 1024 lrck cycles (1024/fs). (2) digital output delay from the digital input is called the group delay (gd). (3) if the soft mute is cancelled before attenuating to ? after starting the operation, the attenuation is discontinued and returned to 0db by the same number of clock cycles. asahi kasei [AK4122] ms0267-e-02 2004/07 - 23 - ? de-emphasis filter control the AK4122 includes the digital de-emphasis filter (tc=50/15 s) by iir filter corresponding to three sampling frequencies (32khz, 44.1khz and 48khz). (1) when input port is dir when the input port is dir and deau bit = ?1?, the de-em phasis filter is enabled automa tically by sampling frequency (fs3-0 bit) and pre-emphasis information in the channel status. dem1-0 bits can control the de-emphasis filter when deau bit = ?0?. when the de-emphasis filter is off, the internal de-emphasis filter is bypassed. when pem bit = ?0?, the internal de-emphasis filter is always bypassed. pem fs3 fs2 fs1 fs0 mode 1 0 0 0 0 44.1khz 1 0 0 1 0 48khz 1 0 0 1 1 32khz 1 (others) off 0 x x x x off table 11. de-emphasis auto control (deau bit = ?1?) pem dem1 dem0 mode 1 0 0 44.1khz 1 0 1 off default 1 1 0 48khz 1 1 1 32khz table 12. de-emphasis manual control (deau bit = ?0?) (2) when input port is port1 or port2 when port1 or port2 is selected as input port, dem1-0 b its can control the de-emphasis filter even if deau bit = ?0? or deau bit = ?1?. in this case, the de-emphasis filter cannot enable automatically. when th e de-emphasis filter is off, the internal de-emphasis filter is bypassed. dem1 dem0 mode 0 0 44.1khz 0 1 off default 1 0 48khz 1 1 32khz table 13. de-emphasis manual control ? system reset and power-down the AK4122 has a full power-down mode for all circuits that is activated by the pdn pin, and a partial power-down mode activated by the pwn bit. the AK4122 should be reset once at power-up by bringing pdn pin = ?l?. pdn pin: all analog and digital circuits are placed in power-dow n and reset modes by bringi ng pdn pin = ?l?. all the registers are initialized and clocks are stopped. read/write operations to the registers are disabled. pwn bit (address 00h; d0): unlike the pdn pin operation described a bove, internal registers and mode se ttings are not initialized. read/write operations to the registers are enabled. asahi kasei [AK4122] ms0267-e-02 2004/07 - 24 - ? system reset bringing the pdn pin = ?l? sets the AK4122 power-down mode and initializes the digital filter. when pdn pin = ?l?, the sdto output is ?l?. the AK4122 should be reset once by bringing pdn pin = ?l? upon power-up. the sdto is valid from less than 100ms after the rising of pdn after clocks are supplied, and until then, outputs ?l?. after the rising of pdn pin, the sdtio pin is input pin. external clocks (input / output port) sdto (internal state) pdn don?t care (stable) don?t care power-down normal operation pll locktime & fs detection ?0? data < 100msec normal data power-down ?0? data figure 13. system reset ? sequence of changing clocks the recommended sequence of changing clocks is shown as figur e 14. the internal reset is executed when the input or the output clocks are changed. the sdto is placed ?0? during reset. within 100ms, the sdto outputs normal data. when the frequency transition occurs gradually without the pha se change, the output data may have large distortion for several seconds. then, to output normal data within 100ms, a reset by pdn pin = ?l? or pwn bit = ?0? is recommended when clocks are changed. pll locktime & fs detection power down external clocks (input port or output port) state 1 (44.1khz) sdtio / sdto (internal state) normal operation normal operation state 2 (48khz) (unknown) < 100msec smute (note2, recommended) 1024/fso a tt.level 0db - db normal data normal data 1024/fso pdn pin or pwn bit note1 figure 14. sequence of changing clocks note 1. the data on sdto may cause click noise. if sdti or sdtio is ?0? from gd before pdn pin goes ?l?, the data on sdto keeps ?0? then no unknown data is output. note 2. smute can remove the unknown data. asahi kasei [AK4122] ms0267-e-02 2004/07 - 25 - ? 96khz clock recovery the on-chip, low jitter pll of dir has a wide lock range of 32khz to 96khz a nd a lock time of less than 20ms. the AK4122 has a sampling frequency detect function (32khz, 44. 1khz, 48khz, 88.2khz, 96khz) that uses either clock comparison against the mclk2 or omclk frequency or the cha nnel status information. the pll loses lock when the received sync interval is incorrect. ? biphase input four receiver inputs (rx1-4) of dir are available. each input includes an amp lifier for unbalance lo ads that can accept 200mvpp or greater signal. the ips1-0 bits select the receiver channel (table 14). ips1 ips0 input data 0 0 rx1 0 1 rx2 1 0 rx3 1 1 rx4 default table 14. recovery data select ? biphase output the AK4122 can output the through data from the digital receive r inputs (rx1-4) to the tx pin. the ops1-0 bits can select the source of the output from the tx pin. tx output can be stopped by txe bit. AK4122 does not have the tx output buffer (line driver), the tx pin cannot drive the 75 ? coaxial cable directly. ops1 ops0 output data 0 0 rx1 0 1 rx2 1 0 rx3 1 1 rx4 default table 15. output data select for tx asahi kasei [AK4122] ms0267-e-02 2004/07 - 26 - ? biphase signal input circuit rx AK4122 0.1uf 75 ? coax 75 ? figure 15. consumer input circuit (coaxial input) note 1: coax input only : if a coupling level to this input from the next rx i nput line pattern exceeds 50mv, an incorrect operation may occur. in this case, it is possible to lower the coupling level by adding this decoupling capacitor. note 2: ground of the rca connector and terminator should be connected to avss of the AK4122 with low impedance on pc board. rx AK4122 470 o/e optical receiver optical fiber 3.3v figure 16. consumer input circuit (opti cal input, using 3.3v optical receiver) when using coaxial input, the input level of the rx line is small. care must be taken to reduce, crosstalk among rx input lines by inserting a shield pattern between them. asahi kasei [AK4122] ms0267-e-02 2004/07 - 27 - ? sampling frequency and pre-emphasis detection the AK4122 has two methods for detecting the sampling freque ncy. the sampling frequency is detected by comparing the recovered clock to the mclk2 or omclk frequency, and the detected frequency is reported on fs3-0 bits. xtl1-0 bits, icks1-0 bits and ocks1-0 bits can select referen ce mclk2 and omclk (table 16). when xtl1-0 bits = ?11?, the sampling frequency is detected by the channel status sampling frequency information. the detected frequency is reported on fs3-0 bits. the default values of fs3-0 bits are ?0001?. in case of detecting the sampling frequency by mclk when dir is used, mclk (mclk2 or omclk) of selected output port (port2 or port3) should be input. mclk2 or omclk xtl1 xtl0 icks1 / ocks1 icks0 / ocks0 mclk frequency 0 0 11.2896mhz 0 1 22.5792mhz 1 0 16.9344mhz 0 0 1 1 33.8688mhz 0 0 12.288mhz 0 1 24.576mhz 1 0 18.432mhz 0 1 1 1 36.864mhz 0 0 24.576mhz 0 1 n/a 1 0 36.864mhz 1 0 1 1 n/a 1 1 - - use channel status default table 16. reference mclk frequency except xtl1-0 bit = ? 11? xtl1-0 bit = ?11? register output consumer mode (note 2) professional mode fs3 fs2 fs1 fs0 fs clock comparison (note 1) byte3 bit3,2,1,0 byte0 bit7,6 byte4 bit6,5,4,3 0 0 0 0 44.1khz 3% 0000 01 0000 0 0 0 1 reserved - 0001 (others) 0000 0 0 1 0 48khz 3% 0010 10 0000 0 0 1 1 32khz 3% 0011 11 0000 1 0 0 0 88.2khz 3% (1000) 00 1010 1 0 1 0 96khz 3% (1010) 00 0010 table 17. fs information note 1. at least 3% range is identified as the value in the table 17. in case of an intermediate frequency of these two, fs3-0 bits indicate the nearer value. when the frequency is much larger than 96khz or much smaller than 32khz, fs3-0 bits may indicate ?1100?, ?1110? or ?0001?. note 2. in consumer mode, byte3 bit3-0 are copied to fs3-0. the pre-emphasis information is detected and reported on the pem bit. this information is extracted from channel 1 by default (cs12 bit = ?0?). it can be switched to channe l 2 by changing the cs12 bit in the control register. consumer mode professional mode pem bit pre-emphasis byte0 bit3,4,5 byte0 bit2,3,4 0 off 0x100 100 1 on 0x100 100 table 18. pem information asahi kasei [AK4122] ms0267-e-02 2004/07 - 28 - ? interrupt handling for dir there are nine events that cause the int2-0 pins to go ?h?. 1. unlck: pll unlock state detection ?1? when the pll loses lock. the AK4122 loses lock when the distance between two preambles is not correct or when those preambles are not correct. 2. par: parity error or biphase coding error detection ?1? when parity error or biphase coding erro r is detected, updated every sub-frame cycle. 3. auto: non-pcm or dts-cd bit stream detection the or function of npcm and dtscd bits is output to the auto bit. 4. v: validity flag detection ?1? when validity flag is detected . updated every sub-frame cycle. 5. audn: non-a udio detection ?1? when the ?audn? bit in recovered channel stat us indicates ?1?. updated every block cycle. 6. stc: sampling frequency or pre- emphasis information change detection ?1? when fs3-0 or pem bit changes. reading 07h register resets it. 7. qint: u bit (q-subcode) sync flag ?1? when the q-subcode differs from old one, and stays ?1? until this register is read. updated every sync code cycle for q-subcode. reading 07h register resets it. 8. cint: channel status sync flag ?1? when received c bits differ from old ones, and st ays ?1? until this register is read. updated every block cycle. reading 07h register resets it. 9. dat: dat start id detection when the category code shows dat, ?1? when the star t id of dat is detected. reading 08h register resets it. int1-0 pins output an or?ed signal based on the above nine interrupt events. when masked, the interrupt event does not affect the operation of the int1-0 pins (the masks do not affect the registers (unlck, par, etc.) themselves). once int0 pin goes to ?h?, it maintains ?h? for 1024 cycles (this value can be changed by the efh1-0 bits) after all events not masked by mask bits are cleared. int1 pin immedi ately goes to ?l? when t hose events are cleared. int2 pin output a state change on the above 1 5 and an or?ed signal based on the above 6 9. it stays ?h? until 07h and 08h registers are read. mask bits are shared with int0. unlck, auto, v and audn bits indicate the interrupt status events above in real time. once par, stc, qint or cint and dat bit goes to ?1?, it stays ?1? until the register is read. when the AK4122 loses lock, the channel stat us bits are initialized. in this initial state, int0 and int2 outputs the or?ed signal between unlck and par bits. int1 outputs the or ?ed signal to auto, v and audn. int2-0 pins are ?l? when the dir is not selected. when dir is used as input port and the pll loses lock (unlock state), the output data is muted automatically. when amute bit = ?1?, sdtio and sdto are muted automatically when the AK4122 detects unlock, non-audio or non-pcm/dts-cd. after the interrupt ev ents are cleared, mute is cancelled au tomatically. when amute bit = ?0?, sdtio and sdto outputs ?l? when the pll loses lock (unloc k state), and outputs data when other errors (par, auto etc.). asahi kasei [AK4122] ms0267-e-02 2004/07 - 29 - (1) unlck, par, auto, v and audn bits hold ?1? interrupt (unlck, par, auto, v, audn) int0 pin int1 pin int2 pin register 07h read 07h ?0? hold time (max:4096/fs) ?0? hold time = 0 bick, lrck (unlck) bick, lrck (except unlck) sdtio / sdto (amute = ?1?) (unlck, auto, v, audn) sdtio / sdto (amute = ?0?) (auto, v, audn) sdtio / sdto (par error) free run fs : around 20khz sdtio / sdto (amute = ?0?) (unlck) mute ?l? output previous data : normal operation figure 17. int2-0 timing (unlck, par, auto, v, audn bits) asahi kasei [AK4122] ms0267-e-02 2004/07 - 30 - (2) stc, cint and qint bits interrupt (stc, cint, qint) int0 pin int1 pin int2 pin register 07h read 07h bick, lrc k sdtio / sdto interrupt (fs3-0, pem, c-bit, q-sub) ?0? hold ?1? ?0? (1) (2) : normal operation hold ?1? ?0? (1) (2) figure 18. int2-0 timing (stc, cint, qint bits) (1) hold time : max. 4096/fs (2) hold time = 0 asahi kasei [AK4122] ms0267-e-02 2004/07 - 31 - (3) dat bit interrupt (dat) int0 pin int1 pin int2 pin register 08h read 08h bick, lrc k sdtio / sdto ?0? hold ?1? ?0? (1) (2) : normal operation hold ?1? ?0? (1) (2) figure 19. int2-0 timing (dat bit) (1) hold time : max. 4096/fs (2) hold time = 0 asahi kasei [AK4122] ms0267-e-02 2004/07 - 32 - int0/1 pin ="h" no ye s ye s initialize pd pin ="l" to "h" read 07h, 08h mute sdtio / sdto read 07h, 08h no (each error handling) read 07h, 08h (resets registers) int0/1 pin ="h" release muting figure 20. interrupt handling sequence example 1 asahi kasei [AK4122] ms0267-e-02 2004/07 - 33 - int1 pin ="h" no ye s initialize pd pin ="l" to "h" read 07h read 07h and detect qsub= ?1? no (read q-buffer) new data is valid int1 pin ="l" qcrc = ?0? yes yes new data is invalid no figure 21. interrupt handling sequence example 2 asahi kasei [AK4122] ms0267-e-02 2004/07 - 34 - ? q-subcode buffers the dir of the AK4122 has a q-subcode buffer for cd app lication. the AK4122 takes q-subcode into registers under the following conditions: 1) the sync word (s0, s1) consists of at least 16 ?0?s. 2) the start bit is ?1?. 3) those 7-bits q-w follows to the start bit. 4) the distance between two start bits is 8-16 bits. the qint bit in the control register goes ?1? when the new q-subcode differs from old one, and goes ?0? when qint bit is read. 1 2 3 4 5 6 7 8 * s0 0 0 0 0 0 0 0 0 0? s1 0 0 0 0 0 0 0 0 0? s2 1 q2 r2 s2 t2 u2 v2 w2 0? s3 1 q3 r3 s3 t3 u3 v3 w3 0? : : : : : : : : : : s97 1 q97 r97 s97 t97 u97 v97 w97 0? s0 0 0 0 0 0 0 0 0 0? s1 0 0 0 0 0 0 0 0 0? s2 1 q2 r2 s2 t2 u2 v2 w2 0? s3 1 q3 r3 s3 t3 u3 v3 w3 0? : : : : : : : : : : (*) number of ?0? : min=0; max=8. figure 22. configuration of u-bit(cd) q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15 q16 q17 q18 q19 q20 q21 q22 q23 q24 q25 ctrl adrs track number index q26 q27 q28 q29 q30 q31 q32 q33 q34 q35 q36 q37 q38 q39 q40 q41 q42 q43 q44 q45 q46 q47 q48 q49 minute second frame q50 q51 q52 q53 q54 q55 q56 q57 q58 q59 q60 q61 q62 q63 q64 q65 q66 q67 q68 q69 q70 q71 q72 q73 zero absolute minute absolute second q74 q75 q76 q77 q78 q79 q80 q81 q82 q83 q84 q85 q86 q87 q88 q89 q90 q91 q92 q93 q94 q95 q96 q97 absolute frame crc g(x)=x 16 +x 12 +x 5 +1 figure 23. q-subcode addr register name d7 d6 d5 d4 d3 d2 d1 d0 13h q-subcode address / control q9 q8 q3 q2 14h q-subcode track q17 q16 q11 q10 15h q-subcode index 16h q-subcode minute 17h q-subcode second 18h q-subcode frame 19h q-subcode zero 1ah q-subcode abs minute 1bh q-subcode abs second 1ch q-subcode abs frame q81 q80 q75 q74 figure 24. q-subcode register map q asahi kasei [AK4122] ms0267-e-02 2004/07 - 35 - ? non-pcm (ac-3, mpeg, etc.) and dts-cd bitstream detection the dir of the AK4122 has a non-pcm steam auto-detection function. when the 32-bit mode non-pcm preamble based on dolby ?ac-3 data stream in iec60958 interface? is de tected, the npcm bit goes to ?1?. the 96-bit sync code consists of 0x0000, 0x0000, 0x0000, 0x0000, 0xf872 and 0x4e1f. detection of this pattern will set the npcm to ?1?. once the npcm is set to ?1?, it will re main ?1? until 4096 frames pass through the chip without an additional sync pattern being detected (timing diagram: figure 27 and figure 28). when those preambles are detected, the burst preambles pc and pd (pc: burst information, pd: length code; refer to table 22, 23) that follow those sync codes are stored to registers. the AK4122 also has a dts-cd bitstream auto-detection function. when AK4122 detects dts-cd bitstream, the dtscd bit goes to ?1?. if the next sync code does not occu r within 4096 frames, the dtscd bit goes to ?0? until either the AK4122 detects the stream again. or?ed value of the npcm and dtscd bits are output to the auto bit. the AK4122 detects 14bit sync word and 16bit sync word of a dt s-cd bitstream, the detection function can be set on/off by dts14 and dts16 bit. ? serial control interface the internal registers may be either written or read by the 4-wire p interface pins: csn, cclk, cdti & cdto. the data on this interface consists of chip a ddress (2bits, c1/0 are fixed to ?00?), r ead/write (1bit), register address (msb first, 5bits) and control data (msb first, 8bits). address and data is clocked in on the rising edge of cclk and data is clocked out on the falling edge. for write operations, data is latched after the 16th rising edge of cclk, after a high-to-low transition of csn. for read operations, the cdto output goes to high impedance after a low-to-high transition of csn. the maximum speed of cclk is 5mhz. th e chip address is fixed to ?00?. the access to the chip address except for ?00? is invalid. pdn pin = ?l? resets the registers to their default va lues. read/write can be access without mclk, bick and , lrck. csn cclk cdti 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 c1 c0 r/w a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 cdto hi-z write cdti c1 c0 r/w a4 a3 a2 a1 a0 cdto hi-z read d7 d6 d5 d4 d3 d2 d1 d0 hi-z c1 - c0 : chip address (fixed to "00") r/w : read / write ("1" : write, "0" : read) a4 - a0 : register address d7 - d0 : control data figure 25. control i/f timing asahi kasei [AK4122] ms0267-e-02 2004/07 - 36 - ? register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h pdn & mode control xtl1 xtl0 txe smute deau dem1 dem0 pwn 01h selector & clock control byps os el isel1 isel0 icks1 icks0 ocks1 ocks0 02h audio interface format 0 0 0 odif idif1 idif0 dif1 dif0 03h dir control cs12 amute efh1 efh0 ips1 ips0 ops1 ops0 04h int0 mask mulk0 mpar0 maut0 mv0 maud0 mstc0 mcit0 mqit0 05h int1 mask mulk1 mpar1 maut1 mv1 maud1 mstc1 mcit1 mqit1 06h dat mask & dts detect 0 0 0 0 dts16 dts14 mdat1 mdat0 07h receiver status 0 unlck par auto v audn stc cint qint 08h receiver status 1 dat dtscd npcm pem fs3 fs2 fs1 fs0 09h receiver status 2 0 0 0 0 0 0 ccrc qcrc 0ah rx channel status byte 0 cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 0bh rx channel status byte 1 cr15 cr14 cr13 cr12 cr11 cr10 cr9 cr8 0ch rx channel status byte 2 cr23 cr22 cr21 cr20 cr19 cr18 cr17 cr16 0dh rx channel status byte 3 cr31 cr30 cr29 cr28 cr27 cr26 cr25 cr24 0eh rx channel status byte 4 cr39 cr38 cr37 cr36 cr35 cr34 cr33 cr32 0fh burst preamble pc byte 0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 10h burst preamble pc byte 1 pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 11h burst preamble pd byte 0 pd 7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 12h burst preamble pd byte 1 pd 15 pd14 pd13 pd12 pd11 pd10 pd9 pd8 13h q-subcode address / control q9 q8 q7 q6 q5 q4 q3 q2 14h q-subcode track q17 q 16 q15 q14 q13 q12 q11 q10 15h q-subcode index q25 q 24 q23 q22 q21 q20 q19 q18 16h q-subcode minute q33 q 32 q31 q30 q29 q28 q27 q26 17h q-subcode second q41 q 40 q39 q38 q37 q36 q35 q34 18h q-subcode frame q49 q 48 q47 q46 q45 q44 q43 q42 19h q-subcode zero q57 q 56 q55 q54 q53 q52 q51 q50 1ah q-subcode abs minute q65 q64 q63 q62 q61 q60 q59 q58 1bh q-subcode abs second q73 q72 q71 q70 q69 q68 q67 q66 1ch q-subcode abs frame q81 q80 q79 q78 q77 q76 q75 q74 pdn pin = ?l? resets the registers to their default values. when port1 or port2 are selected as input port, the status registers (07h 1ch) are initialized. note. unused bits must contain a ?0? value. note. for addresses from 1dh 1fh, data must not be written. asahi kasei [AK4122] ms0267-e-02 2004/07 - 37 - ? register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h pdn & mode control xtl1 xtl0 txe smute deau dem1 dem0 pwn r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 1 1 1 0 0 0 1 1 pwn: power down control 0 : power down 1 : normal operation (default) ?0? powers down all sections. the contents of all register are not initialized and enabled to write to the registers. the internal registers (00h 06h) are not initialized, however, the status registers (07h 1ch) are initialized. read/write operations to the registers are enabled. dem1-0: de-emphasis control (table 12, 13) initial values are ?01?. deau: de-emphasis auto control 0 : disable (default) 1 : enable when deau bit = ?1?, the de-emphasis filter is enabled automatically by sampling frequency and pre-emphasis information in the channel status. smute: soft mute control 0 : normal operation (default) 1 : sdtio and sdto soft mute when smute bit = ?1?, sdto and sdtio outputs ?l?. txe: tx output enable 0 : disable, tx outputs ?l?. 1 : enable (default) xtl1-0: reference mclk frequency select (table 16) initial values are ?11?. asahi kasei [AK4122] ms0267-e-02 2004/07 - 38 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h selector & clock control byps os el isel1 isel0 icks1 icks0 ocks1 ocks0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 0 1 0 1 0 ocks1-0: omclk frequency select for master mode (table 5) initial values are ?10?. icks1-0: mclk2 frequency select for master mode (table 4) initial values are ?10?. isel1-0: input port select initial values are ?00?. isel1 isel0 input port 0 0 port1 0 1 port2 1 0 dir 1 1 n/a default table 19. input port select osel: output port select initial values are ?0?. osel output port 0 port3 1 port2 default table 20. output port select byps: select bypass mode 0 : src mode (default) 1 : bypass mode when byps bit = ?1?, the AK4122 outputs the clocks (bick, lrck) and data that is input by input port without src. asahi kasei [AK4122] ms0267-e-02 2004/07 - 39 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h audio interface format 0 0 0 odif idif1 idif0 dif1 dif0 r/w rd rd rd r/ w r/w r/w r/w r/w default 0 0 0 0 0 1 0 1 dif1-0: audio interface format for port1 (table 8) initial values are ?01?. idif1-0: audio interface format for port2 (table 9) initial values are ?01?. odif: audio interface format for port3 (table 10) initial values are ?0?. addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h dir control cs12 amute efh1 efh0 ips1 ips0 ops1 ops0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 1 0 1 0 0 0 0 ops1-0: output through data select for tx (table 15) initial values are ?00?. ips1-0: input recovery data select (table 14) initial values are ?00?. efh1-0: interrupt 0 pin hold count select initial values are ?01?. lrck of table 21 is dir?s lrck, the hold time scales with 1/fs. efh1 efh0 hold count 0 0 512lrck 0 1 1024lrck 1 0 2048lrck 1 1 4096lrck default table 21. hold count select amute: auto mute control 0 : normal operation 1 : auto mute (default) when amute bit = ?1?, sdtio and sdto are muted automatically when the AK4122 detects unlock, non-audio or non-pcm/dts-cd. cs12: channel status select 0 : channel 1 (default) 1 : channel 2 this bit selects that channel status is used to derive c-bit buffers, audn, pem, fs3-0, pc, pd and crc. asahi kasei [AK4122] ms0267-e-02 2004/07 - 40 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h int0 mask mulk0 mpar0 maut0 mv0 maud0 mstc0 mcit0 mqit0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 1 1 1 1 1 1 mqit0: mask enable for qint bit 0 : mask disable 1 : mask enable mcit0: mask enable for cint bit 0 : mask disable 1 : mask enable mstc0: mask enable for stc bit 0 : mask disable 1 : mask enable maud0: mask enable for audn bit 0 : mask disable 1 : mask enable mv0: mask enable for v bit 0 : mask disable 1 : mask enable maut0: mask enable for auto bit 0 : mask disable 1 : mask enable mpar0: mask enable for par bit 0 : mask disable 1 : mask enable mulk0: mask enable for unlck bit 0 : mask disable 1 : mask enable the factor which mask bit is set to ?0? affects int0 and int2 pins operation. asahi kasei [AK4122] ms0267-e-02 2004/07 - 41 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h int1 mask mulk1 mpar1 maut1 mv1 maud1 mstc1 mcit1 mqit1 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 1 1 0 0 0 1 1 1 mqit1: mask enable for qint bit 0 : mask disable 1 : mask enable mcit1: mask enable for cint bit 0 : mask disable 1 : mask enable mstc1: mask enable for stc bit 0 : mask disable 1 : mask enable maud1: mask enable for audn bit 0 : mask disable 1 : mask enable mv1: mask enable for v bit 0 : mask disable 1 : mask enable maut1: mask enable for auto bit 0 : mask disable 1 : mask enable mpar1: mask enable for par bit 0 : mask disable 1 : mask enable mulk1: mask enable for unlck bit 0 : mask disable 1 : mask enable the factor which mask bit is set to ?0? affects int1 pin operation. asahi kasei [AK4122] ms0267-e-02 2004/07 - 42 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h dat mask & dts detect 0 0 0 0 dts16 dts14 mdat1 mdat0 r/w rd rd rd rd r/w r/w r/w r/w default 0 0 0 0 1 1 1 1 mdat0: mask enable for dat bit 0 : mask disable 1 : mask enable the factor which mask bit is set to ?0? affects int0 and int2 pins operation. mdat1: mask enable for dat bit 0 : mask disable 1 : mask enable the factor which mask bit is set to ?0? affects int1 pin operation. dts14: dts-cd 14bit sync word detect 0 : no detect 1 : detect (default) dts16: dst-cd 16bit sync word detect 0 : no detect 1 : detect (default) asahi kasei [AK4122] ms0267-e-02 2004/07 - 43 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h receiver status 0 unlck par auto v audn stc cint qint r/w rd rd rd rd rd rd rd rd default 0 0 0 0 0 0 0 0 qint: q-subcode buffer interrupt 0 : no change 1 : changed this bit goes to ?1? when q-subcode stored in register addresses 13h to 1ch is updated. cint: channel status buffer interrupt 0 : no change 1 : changed this bit goes to ?1? when c-bit stored in register addresses 0ah to 0eh changes. stc: sampling frequency or pre-em phasis information change detection 0 : no detect 1 : detect this bit goes to ?1? when either the fs3-0 or pem bit changes. audn: audio bit output 0 : audio 1 : non audio this bit is made by encoding channel status bits. v: validity bit 0 : valid 1 : invalid auto: non-pcm or dts-cd bit steam auto detection 0 : no detect 1 : detect this bit outputs the or?ed value of npcm and dtscd bits. par: parity error or bi-phase error status 0 : no error 1 : error this bit goes to ?1? if a parity error or biphase error is detected in the sub-frame. unlck: pll lock status 0 : lock 1 : unlock qint, cint and stc bits are initialized when 07h is read. asahi kasei [AK4122] ms0267-e-02 2004/07 - 44 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h receiver status 1 dat dtscd npcm pem fs3 fs2 fs1 fs0 r/w rd rd rd rd rd rd rd rd default 0 0 0 0 0 0 0 1 fs3-0: sampling frequency detection (table 17) pem: pre-emphasis detect (table 18) 0 : off 1 : on this bit is made by encoding the channel status bits. npcm: non-pcm bit stream auto detection 0 : no detect 1 : detect dtscd: dts-cd bit stream auto detect 0 : no detect 1 : detect dat: dat start id detect 0 : no detect 1 : detect when the category code shows dat, ?1? when the star t id of dat is detected. reading 08h register resets it. dat bit is initialized when 08h is read. addr register name d7 d6 d5 d4 d3 d2 d1 d0 09h receiver status 2 0 0 0 0 0 0 ccrc qcrc r/w rd rd rd rd rd rd rd rd default 0 0 0 0 0 0 0 0 qcrc: cyclic redundancy check for q-subcode 0 : no error 1 : error ccrc: cyclic redundancy check for channel status 0 : no error 1 : error this bit is enabled only in professional mode and only for the channel selected by the cs12 bit. asahi kasei [AK4122] ms0267-e-02 2004/07 - 45 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah rx channel status byte 0 cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 0bh rx channel status byte 1 cr15 cr14 cr13 cr12 cr11 cr10 cr9 cr8 0ch rx channel status byte 2 cr23 cr22 cr21 cr20 cr19 cr18 cr17 cr16 0dh rx channel status byte 3 cr31 cr30 cr29 cr28 cr27 cr26 cr25 cr24 0eh rx channel status byte 4 cr39 cr38 cr37 cr36 cr35 cr34 cr33 cr32 r/w rd default not initialized cr39-0: receiver channe l status byte 4-0 all 40 bits are updated at the same time every block (192 frames) cycle. addr register name d7 d6 d5 d4 d3 d2 d1 d0 0fh burst preamble pc byte 0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 10h burst preamble pc byte 1 pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 11h burst preamble pd byte 0 pd 7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 12h burst preamble pd byte 1 pd 15 pd14 pd13 pd12 pd11 pd10 pd9 pd8 r/w rd default not initialized pc15-0: burst preamble pc byte 0 and 1 pd15-0: burst preamble pd byte 0 and 1 addr register name d7 d6 d5 d4 d3 d2 d1 d0 13h q-subcode address / control q9 q8 q7 q6 q5 q4 q3 q2 14h q-subcode track q17 q 16 q15 q14 q13 q12 q11 q10 15h q-subcode index q25 q 24 q23 q22 q21 q20 q19 q18 16h q-subcode minute q33 q 32 q31 q30 q29 q28 q27 q26 17h q-subcode second q41 q 40 q39 q38 q37 q36 q35 q34 18h q-subcode frame q49 q 48 q47 q46 q45 q44 q43 q42 19h q-subcode zero q57 q 56 q55 q54 q53 q52 q51 q50 1ah q-subcode abs minute q65 q64 q63 q62 q61 q60 q59 q58 1bh q-subcode abs second q73 q72 q71 q70 q69 q68 q67 q66 1ch q-subcode abs frame q81 q80 q79 q78 q77 q76 q75 q74 r/w rd default not initialized q81-2: q-subcode all 80 bits are updated at the same time every sync code cycle for q-subcode. asahi kasei [AK4122] ms0267-e-02 2004/07 - 46 - ? burst preambles in non-pcm bitstreams 0 16 bits of bitstream 34 7 811 12 27 28 29 30 31 preamble aux. lsb msb v u c p sub-frame of iec60958 015 pa pb pc pd burst_payload stuffing repetition time of the burst figure 26. data structure of iec60958 preamble word length of field contents value pa 16 bits sync word 1 0xf872 pb 16 bits sync word 2 0x4e1f pc 16 bits burst info see table 23 pd 16 bits length code numbers of bits table 22. burst preamble word asahi kasei [AK4122] ms0267-e-02 2004/07 - 47 - bits of pc value contents repetition time of burst in iec60958 frames 0-4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16-31 data type null data dolby ac-3 data reserved pause mpeg-1 layer1 data mpeg-1 layer2 or 3 data or mpeg-2 without extension mpeg-2 data with extension mpeg-2 aac adts mpeg-2, layer1 low sample rate mpeg-2, layer2 or 3 low sample rate reserved dts type i dts type ii dts type iii atrac atrac2/3 reserved 4096 1536 384 1152 1152 1024 384 1152 512 1024 2048 512 1024 5, 6 0 reserved, shall be set to ?0? 7 0 1 error-flag indicating a valid burst_payload error-flag indicating that th e burst_payload may contain errors 8-12 data type dependent info 13-15 0 bit stream number, shall be set to ?0? table 23. field of burst information pc asahi kasei [AK4122] ms0267-e-02 2004/07 - 48 - ? non-pcm bitstream timing (1) when non-pcm preamble does not arrive within 4096 frames pd 3 pc 3 pa pc 1 pd 1 pb pa pc 2 pd 2 pb pa pc 3 pd 3 pb ?0? pc 1 pc 2 ?0? pd 1 pd 2 pdn pin bit stream a uto bit pc register pd registe r repetition time >4096 frames figure 27. timing example 1 (2) when non-pcm bitstream stops (when mulk0=0) pd n pc n pa pc 1 pd 1 pb stop pa pc n pd n pb pc 0 pc 1 pd 0 pd 1 int0 pin bit stream a uto bit pc register pd registe r int0 hold time 2~3 syncs (b,m or w) <20ms (lock time) asahi kasei [AK4122] ms0267-e-02 2004/07 - 50 - 1. grounding and power supply decoupling the AK4122 requires careful attention to power supply and grounding arrangements. alternatively if avdd and dvdd are supplied separately, the power up sequence is not critical. avss, bvss and dvss of the AK4122 must be connected to analog ground plane. system analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as near to the AK4122 as possible, with the small value ceramic capacitor being the nearest. 2. pll loop-filter the c1 (2.2 f) and r1 (470 ? ) should be connected in series and attached between filt pin and avss in parallel with c2 (2.2nf). please be careful the noise onto the filt pin. AK4122 c1 r1 filt a vss c2 parameter recommended value accuracy r1 470 ? ? 5% +5% c1 2.2 f ? 50% +50% c2 2.2nf ? 50% +50% note: the accuracy includes temperature dependence. figure 30. loop filter for src the r2 (12k ? ) should be connected in series and attached between r pin and avss. please be careful the noise onto the r pin. AK4122 r2 r a vss parameter recommended value accuracy r2 12k ? ? 5% +5% note: the accuracy includes temperature dependence. figure 31. loop filter for dir asahi kasei [AK4122] ms0267-e-02 2004/07 - 51 - package 1 12 48 13 7.0 9.0 0.2 7.0 9.0 0.2 0.22 0.08 48pin lqfp(unit: mm) 0.10 37 24 25 36 0.16 0.07 1.40 0.05 0.13 0.13 1.70max 0 10 0.10 0.5 0.2 0.5 m ? material & lead finish package molding compound: epoxy lead frame material: cu lead frame surface treatme nt: solder (pb free) plate asahi kasei [AK4122] ms0267-e-02 2004/07 - 52 - marking 1 akm AK4122vq xxxxxxx xxxxxxxx: date code identifier asahi kasei [AK4122] ms0267-e-02 2004/07 - 53 - revision history date (yy/mm/dd) revision reason page contents 03/10/03 00 first edition 04/01/27 01 spec change 10, 11 switching characteristics audio interface timing bick1/bick2/bick period@slave mode: min 160ns 1/64/fs add spec 9 add filter characteristics 04/07/23 02 add spec 16, 18 add a sentence: ?the dif1-0 bits of the port1 should be set a value except ?10? (i2s co mpatible) when the dir is selected as an input port.? important notice ? these products and their specifications are subjec t to change without notice. before considering any use or application, consult the asahi kasei micros ystems co., ltd. (akm) sales office or authorized distributor concerning their current status. ? akm assumes no liability for infringement of any pat ent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of expor t pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system , and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: a. a hazard related device or system is one des igned or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expect ed to result in loss of life or in significant injury or damage to person or property. b. a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the lo ss of the safety or effe ctiveness of the device or system containing it, and which must therefor e meet very high standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an akm product who dist ributes, disposes of, or otherwise places the product with a third party to notify that party in advanc e of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification. |
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